| 摘要 |
PURPOSE:To cancel the phase error, by providing the result of comparison outputted through a comparison circuit to an output holding circuit and making the phase shift equal among plural input signal pairs even with an offset voltage. CONSTITUTION:An output 4 of the comparison circuit 1 is given to one terminal of output transfer gates 10, 12 in common and an output 5 is given to one terminal of output transfer gates 11, 13 in common. A gate of the transfer gates 10, 11 is connected to a clock phi2, the other terminal of the output transfer gate 10 is connected to an input 15 of the 1st output holding circuit 14 and the other terminal of the output transfer gate 11 is connected to an input 16 of said 1st output holding circuit 14. A gate of the output transfer gates 12, 13 is connected to a clock phi4, the other terminal of the output transfer gate 12 is connected to an input 18 of the 2nd output holding circuit 17, and the other terminal of the output transfer gate 13 is connected to an input 19 of the 2nd output holding circuit 17. Q1, Q2 are output terminals of the output holding circuits 14, 17. |
