| 摘要 |
The circuit provides a signal (a) at the application of an interrogation pulse (as) if a change of state has occurred in a one-out-of-n system until the instant of interrogation. Each signal (1 . . . n) of the system is assigned an arrangement having storage capability and comprising two inverters (i1, i2) with feedback and two series-connected transistors (t2, t3) which are both conducting at the instant of interrogation and, thus, produce an unambiguous signal level at a common load resistor (l) only if a change of state has occurred in the system. |
