Integrated CMOS circuit with increased resistance to the latch-up effect

摘要

A CMOS circuit with increased resistance to the latch-up effect comprises a buried layer (112) which has a relatively high impurity density and is situated underneath an MOS device. In a CMOS IC, an MOS is formed directly in a primary semiconductor layer, whereas the second CMOS is formed in a diffused island region (106) inside the primary layer. The buried layer (112) is situated underneath the first MOS and increases the base density of the parasitic bipolar transistors in the region of the first MOS. Since the buried layer (112) is not situated underneath the island region (106), the dielectric strength between the island region (106) and the semiconductor substrate (105) is not limited. <IMAGE>