| 摘要 |
PURPOSE: A system for reducing the power consumption of an FPGA(Field-Programmable Gate Array) is provided to reduce the power consumption used by the entire system by converting the mode of an FPGA to a standby mode if a driving signal is not inputted or a predetermined counting time is over. CONSTITUTION: The system(100) comprises a processor(110) and the FPGA(120). The processor outputs a clock signal and a driving signal. The FPGA comprises a sensing circuit(130), a clock buffer(140), and an internal circuit(150). The sensing circuit comprises a counter outputting a count completion signal after a predetermined counting time is over and a logic outputting an enable signal or a disable signal to the clock buffer depending on the input of the count completion signal or the driving signal. The clock buffer comprises the first to the third clock buffers(141-143) converting the block signal into the first to the third internal clock signals. The internal circuit comprises the first to the third internal circuits(151-153) driving the system by using the first to the third clock signals outputted from the clock buffer.
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