Insulated gate FET with extended gate depth - formed by depositing polycrystalline silicon in grooves of semiconductor substrate along channel between source and drain regions

摘要

The insulated gate FET is formed in a semiconductor substrate and has a source region (10), a drain region (12) and a channel regions (14). The gate (24) has its depth (36) extended into at least one groove in the semiconductor along almost the entire length of the channel between the source and drain regions. The gate is insulated from the channel region by a thin insulating layer (26) which completely covers the interior surface of the grooves, whose depth is greater than their width. The upper surface of the channel region outside the slots is covered by a thin insulating layer itself covered by the gate. The gate is realized in polycrystalline silicon. The transistor fabrication procedure consists in first forming grooves in the semiconductor substrate by reactive ionic etching. The silicon surface is then oxidised to create a thin insulating layer. Finally, polycrystalline silicon is deposited inside the grooves and over the intervals between the grooves. This structure reduces the resistance of the transistor without increasing its surface.