发明名称 ENCODING AND DECODING SYSTEM IN FRAME
摘要 PURPOSE:To miniaturize the device with large scale circuit integration, by using the synchronizing sampling predictive system and the asnchronizing sampling predictive system through switching depending on the magnitude of the synchronizing frequency fluctuation in an NTSC signal and corresponding one encoder for arbitrary picture signals. CONSTITUTION:The inputted picture signal of the NTSC system is applied to an LPF2 to limit the frequency band to a prescribed value, and applied to clock generator 4 and an A/D converter 3, where the synchronizing signal is separated and the signal is converted into a digital signal. The circuit 4 generates the asynchronizing sampling clock and the sampling clock synchronizing-separated from the clock source 5 through switching by the output of a synchronizing/ asynchronizing changeover switch 6. The signal synchronized/asynchronized in this way is decoded at a clock reproducing circuit 24, a signal representing the distinction whether it is synchronizing or asynchronizing sampling is applied to a switch 26, and a signal representing the quantized representing value is applied to an adder 27. Further, the synchronized/asynchronized sampling predictive systems are switched, and one encoder is used for arbitrary picture signals.
申请公布号 JPS58191588(A) 申请公布日期 1983.11.08
申请号 JP19820074513 申请日期 1982.05.06
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 KURODA HIDEO;TAKEGAWA NAOKI
分类号 H04N11/04;H04N7/62 主分类号 H04N11/04
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