| 摘要 |
A circuit for electronic damping of stepper motors capable of generating a pulse train for a wide range of steps such that the pulse train is contained within a period or periods of the resonant frequency of the rotor of the stepper motor to pre-condition for the delayed last step and the last pulse is delayed by a half-period of the resonant frequency. A frequency synthesizer generates a clock signal having a frequency which is an integer multiple of the natural frequency of the rotor of the stepper motor. The clock signal is fed through a gate to a digitally controllable counter which generates an output after one full period of the stepper motor rotor's natural frequency. The output of the digitally controllable counter closes the gate to block the clock signal and triggers a delay circuit which generates the last pulse after a half-period of the natural frequency of the rotor of the stepper motor.
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