| 摘要 |
For generating a working address in a central processing unit of a computer by combining the content of a specified one of a plurality of relocation registers with the content of one of a plurality of general purpose registers that is specified by a datum given to the central processing unit, an addressing system comprises a mode register for producing a register output signal at a time, a decoder for deriving a decoder output signal from the datum, and a selecting circuit responsive to the register and the decoder output signals for selecting one of the relocation registers as the specified relocation register. Preferably, combinations of the signals produced by the mode register and those derived by the decoder from the data specifying at least predetermined ones of the general purpose registers are in one-to-one correspondence to the relocation registers. When the mode register has a plurality of one-bit memory cells, a mode register signal stored in the mode register may be changed by storing a one-bit signal derived from a result of operation of the central processing unit in one of the mode register memory cells that is selected by the decoder output signal.
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