| 摘要 |
PURPOSE:To reduce greatly an erasing period of a color memory, by accelerating a vertical address signal during erasion of the color memory in comparison with the cycle of a normal state. CONSTITUTION:In a normal state, the output signal of an addess converting circuit 4 is supplied to a color memory 2 in the form of a vertical address signal. The circuit 4 converts the vertical address signal produced from a vertical address counter 3 into a state that is frequency divided in response to the number of lines of each color block. In an erasion mode of the memory 2, a signal of several lower bits of the counter 3 is supplied to the memory 2 and used as a vertical address signal. |
