| 摘要 |
PURPOSE:To decrease greatly the time required for the set-up of synchronization, by providing plural code series generating means which shift the phase of the code series and a selecting means which selects each code series obtained from said code series generating means. CONSTITUTION:A specific output is selected from an n-stage shift register 20, and an output is obtained from exclusive OR circuits 22 and 23, respectively. In such a way, three sets of code outputs having about 1/3 phase shift to each other are obtained to a cycle of a pseudo noise code and given to a data selector 24. One of these three sets of codes is delivered via a 1/2-bit shift register 11. These codes disperse adversely receiving signals RXSS through three correlators 1-3 and detect correlations through envelope curve wave detectors 4- 6. A synchronization detecting circuit 19 applies the correlated and detected signal to the selector 24 and has a control to select the code corresponding to said signal. When the synchronization is detected, a clock controlling circuit 18 is controlled to discontinue the searching. Thus a synchronous state is held. |
