发明名称 VECTOR PROCESSOR
摘要 PURPOSE:To improve the efficiency for starting and releasing of an instruction, by detecting the end of reading of a vector register and then releasing an operator and a memory requester. CONSTITUTION:When an instruction is started to transfer a vector data to a vector register from a main storage, the writing is carried out to a vector register 4 from an instruction control unit 3 via a signal line l6 after a memory requester 60 and the vector register unit 4 are actuated. For an addition instruction, a data is read out of the register 4. When the reading is over, reading end signals l402 and l412 are transmitted to an instruction control unit 3. For a storing instruction, a memory requester 61 and the register 4 are actuated to store the instruction via a signal line l420. A reading end signal l422 is transmitted to the unit 3 when the reading of the register 4 is over.
申请公布号 JPS58189770(A) 申请公布日期 1983.11.05
申请号 JP19820070383 申请日期 1982.04.28
申请人 HITACHI SEISAKUSHO KK 发明人 ABE HITOSHI;HATAKEYAMA YASUHIKO
分类号 G06F9/38;G06F15/78;G06F17/16;(IPC1-7):06F15/347 主分类号 G06F9/38
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