| 摘要 |
PURPOSE:To improve both the processing speed and the using efficiency, by holding a machine cycle asignment signal at the requester side until the starting is through with all corresponding banks in case where a request which accesses to plural banks is accepted. CONSTITUTION:When a request 012 accesses to plural banks of a storage device for a data processor in which plural access requester devices share the same storage device, a signal 013 is delivered from an MS priority circuit 01 to set a latch 04. The accepted request signal 012 is supplied to an EX producing circuit 02, and access request signals 021 are successively produced. When all signals 021 are produced, the latch 04 is reset by an end signal 022. The output signal 041 of the latch 04 is transmitted to other access requester devices to suppress all accesses. |
