| 摘要 |
1. A circuit arrangement for the automatic bit rate recognition of an edge-coded information signal which can arrive with two different bit rates, one twice as high as the other, characterized in that a discriminator (DR, Fig.5 or Fig.6) is provided which possesses at least one time element (KS1, KS2 or MF) to which is supplied the edge-coded information signal (S', Sa'') and which on the one hand is triggered by new incoming pulses to monitor for an information signal (Sa'') of the low bit rate and flops back after a first predetermined time (tx) any pulses (G, F) arriving unexpectedly during this first predetermined time (tx) being filtered out via a linking element (UG2) and fed to the first output (Dh) of the discriminator as a criterion (Sh) for the presence of determining information signals of the high bit rate (Sa''), and which time element is triggered after a second predetermined time (ty) following the arrival of a pulse, on the other hand, in order to monitor for an information signal (Sa'') of the high bit rate, provided that no expected new pulse arrives during this second predetermined time (ty), and flops back after a later pulse has arrived, where pulses (M, N) are produced which are fed to the second output (Dt) of the discriminator (DR) as a criterion (St) for the presence of determining information signals of the low bit rate (Sa'). |
