发明名称 DESTRUCTION PREVENTION SYSTEM OF SIGNAL BUS CIRCUIT
摘要 PURPOSE:To prevent plural tri-state elements from being enabled owing to an error of unit insertion and to prevent a signal bus circuit from being destroyed, by providing a unit insertion detecting means, unit insertion error detection means, and unit insertion reporting means. CONSTITUTION:When each unit is capable of mounting up to, for example, three channels, AND circuits 6, 8, and 10 output 1 as far as input terminal CNTBs (11 and 12), (21 and 22), and (31 and 32) are at a level 1 or opened. Therefore, AND circuits 7, 9, and 11 enable the tri-state gates 12-14 once respective unit selection signal FESELs 1-3 go up to 1, and connect respective channel output FEBUSs 1-3 to a common bus FEBUS. Then an AND circuit 15 output 1 to send information showing that there is no unit insertion error to a terminal ERR. If there is an insertion error, a corresponding input of the AND circuit 15, i.e. the output of an AND circuit 6 becomes 0 and the AND circuit 15 also outputs 0, so that the tri-state gate 12 is not enabled.
申请公布号 JPS58184627(A) 申请公布日期 1983.10.28
申请号 JP19820066883 申请日期 1982.04.21
申请人 FUJITSU KK 发明人 KUBO SHINICHI
分类号 G06F3/00;G06F13/40 主分类号 G06F3/00
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