| 摘要 |
PURPOSE:To contrive improvement in degree of integration and flattening of the surface on which a circumferential circuit wiring will be formed by a method wherein the transistor forming region for memory cell is laid out and isolated using the first aperture having a vertical side face which reduces the occupation area. CONSTITUTION:A single layer gate MOS transistor T2, to be used for a circumferential circuit, is arranged in the second aperture H2, whereon regions are laid out by the inclined size face S2 of the field oxide film 2 formed by performing a selective oxidization method, located on a P type silicon substrate 1. A laminated gate MOS transistor T1 to be used for a memory cell is provided in the first aperture H1 which will be laid out by the almost vertical side face S1 formed on the field oxide film 2 using an etching technique. As a result, the improvement in degree of integration can be contrived. |
