| 摘要 |
PURPOSE:To attain a stable and sure clock reproducing operation, by comparing the leading time point of plural clock signals with the generated time point of a pulse phase-synchronized with a bit synchronizing signal, and taking a clock signal rising at first as a decoding clock signal. CONSTITUTION:A clock signal 20 in 5.78MHz is applied to a tapped delay line 16, delayed clock signals 21-1,21-2... are picked up in parallel and applied to phase discriminating circuits 17-1,17-2.... The circuits 17-1,17-2... bring output selection pulses 22-1,22-2... to ''1'' in response to the impressing of a timing signal 26 accurately phase-synchronized with a clock synchronizing signal. While a reset pulse from an NAND gate 18 is ''0'' and the output selection pulses 22-1, 22-2... of the circuits 17-1,17-2... are ''1'', the clock pulse of the signals 21-1, 21-2... rises and goes to ''1'' at a phase discriminating circuit only, the output selection pulse level is brought to ''0'' and the input delay clock signal is taken as a reproducing clock signal. |
