| 摘要 |
PURPOSE:To lock two frequency signals and a timing signal in phase completely, by frequency-dividing and logical-processing an output of an oscillator oscillating a frequency twice the least common multiple of the two transmission frequencies at a required frequency-dividing ratio, in the FSK modulation. CONSTITUTION:Taking a transmission timing frequency as fT and frequencies to space and mark signals as f1, f2 (f1>f2), f1=fT(N+1)/2 and f2=fTN/2 are obtained and an oscillator 301 oscillates the frequency 2f0 being twice the least common multiple f0 of the frequencies f1, f2. The output of the oscillator 301 is frequency-divided by N and (N+1) at frequency dividers 303 and 304, and each output is frequency-divided at frequency dividers 306, 308, and these outputs are applied to an excelusive OR circuit 311, the output of the circuit 311 drives a D flip-flop (FF) 313. Its output 314 holds a prescribed relation with the specific phase of rectangular waves 309, 310 and is inputted to a shift register 315, shifted at a frequency divider 307, and a timing signal is obtained by the exclusive OR between the output and an output of the FF314. |
