| 摘要 |
PURPOSE:To decrease the writing time to a specific bit, by supplying an input data of specific value to a bit having no writing among ternary input data and separating a bit line by a tristate circuit provided in the middle of the bit line. CONSTITUTION:For instance, the writing is carried out only to a memory cell C1 of the 1st bit among plural bits. In this case, a level H or L is supplied to an input data D1 of the 1st bit. While a level M is supplied to other bits which have no writing. Tristate buffer circuits 112, 113- and tristate inverters 122, 123- which are provided in the middle of bit lines B2, -B2, B3 and -B3- excepting the 1st bit line are not actuated and set under a high-impedance output state. Therefore the lines B2, -B2, B3, -B3- are separated from the input data and receive no writing. As a result, the writing is possible easily only to a specific bit in a short time. |
