| 摘要 |
PURPOSE:To prevent the generation of a glitch and higher harmonic components, by providing level interpolating circuits which have switched capacitors to the gates of MOSFETs which have weight corresponding to an input digital signal. CONSTITUTION:The level interpolating circuits are provided to the gates of the MOSFETs Q00-Q0n for preventing the generation of the glitch and highr harmonic components of a D/A convertion output voltage VOUT substantially. Those level interpolating circuits are constituted by utilizing switched capacitor circuits. The input digial signal is integrated by the switched capacitors into a fine staircase digital signal, which is supplied to the gates of the FETs Q00-Q0n. Those FETs Q00-Q0n receiving the level-interpolated digital signal vary in drain currents I0'-2<n>I0' gently. Consequently, a D/A conversion output voltage VOUT' also varies gently to prevent the generation of the glitch and higher harmonic components substantially. |
