发明名称 CONTROLLING AND PROCESSING DEVICE OF LOOP LINE
摘要 <p>PURPOSE:To obtain a device in which no synchronizing signal is lost, even if a many line controlling and processing devices are connected on the same loop line, by providing a synchronizing signal additional circuit to the controlling and processing devices newly. CONSTITUTION:When a start flag detecting circuit 10 detects a start flag F1 of a reception data, an output (c) of start flag detection circuit is made effective to save a message text DATA and an end flag F2 to an FIFO data buffer circuit 11. Simultaneously, a counter circuit 12 is operated, an output d1 operates a synchronizing signal generating circuit 13 and transmits a synchronizing signal SN' to a transmission circuit 4. When the transmission of the signal SN' is finished, a start flag generating circuit 14 is operated with an output d2 of the counter circuit 12 and a start flag F'1 is transmitted. When the transmission of the flag F'1 is finished, then a message text DATA' and an end flag F'2 are transmitted with an output d3 of the counter circuit 12.</p>
申请公布号 JPS58182342(A) 申请公布日期 1983.10.25
申请号 JP19820066013 申请日期 1982.04.19
申请人 NIPPON DENKI KK 发明人 ICHIKAWA FUMIO
分类号 H04L7/00;H04L12/42 主分类号 H04L7/00
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