| 摘要 |
<p>PURPOSE:To prevent word lines from being selected erroneously by connecting a common driving transistor (TR) which is controlled one bit in a group of bits of a row address and TRs which are selected by the all remaining bits while connected to the said TR in common. CONSTITUTION:A decoder circuit consists of a predecoding part 21, main decoding part 22, and clock generating circuit CG. The predecoding part 21 performs NOR operation with the inverted clock of a clock CK passed through an AND circuit. Further, a part 21' for NORing an address bit A6 with the inverted clock is provided. The main decoding part consists of stages of plural driving TRs 21-1-21-3 and the common driving TR21-4 in a reverse pyramid shape and only the common TR is turned off every time the clock falls to hold all nodes N1- N4 at ''H''. Consequently, word lines are prevented from being selected erroneously and the number of TRs is reduced.</p> |
