| 摘要 |
A test circuit (15 or 65), comprised of a plurality of parallel-connected circuit modules (15o-n or 65o-n), in response to both control signals from an associated commercially available automated test set (12), and output data from a test set-accessed read/write memory (14) under test, continuously senses for the presence of valid "one" or "zero" outputs on the data bit lines of the memory throughout a test set-established time window test period. When the memory output from a given data bit line, as applied to only an associated one of the circuit modules, is determined, as normally expected, to be continuously valid during each successive time window test period, a "pass" RESULT signal is generated by that circuit module and continuously applied to the test circuit (12) for flagging at any time between termination of the time window and the end of a given test set-established memory read cycle. Conversely, should the output on any memory data bit line be determined to be invalid (i.e., relative to predetermined threshold voltage limits) at any time during a time window test period, the particular one of the circuit modules (15o-n or 65o-n) receiving that invalid data generates a "fail" RESULT signal that is likewise continuously applied to the test set (12) during the same time interval as for a "pass" RESULT signal.
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