发明名称 ERROR CORRECTING SYSTEM
摘要 PURPOSE:To enable a correction of a 2-bit error without providing a special hardware in a storage device, by storing both the logical value and an address to designate the position of a generated 1-bit error. CONSTITUTION:A data processor 30 performs the writing and reading of data to a main memory MM31 via an interface 32. If a 1-bit error exists when a data 23 is read out of an outer memory, OM33 stores the address AD and syndrome SD24. Thereafter the processor 30 reads out an AD and an SD24 of an 1-bit error from the MM31 in case a 2-bit error is detected when the contents 26 of the AD are read out of the MM31. Then the 1-bit error is corrected by the SD24 of the corresponding address. Then the 2nd bit error is corrected with an SD19 produced from an SD27 generated newly at the MM31 and the stored SD24.
申请公布号 JPS58182762(A) 申请公布日期 1983.10.25
申请号 JP19820065656 申请日期 1982.04.20
申请人 NIPPON DENKI KK 发明人 KOBAYASHI HIDEHIKO
分类号 G06F11/10 主分类号 G06F11/10
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