发明名称 PRE-FETCH CONTROL SYSTEM OF DATA
摘要 PURPOSE:To increase the length of a cable between an input/output device and a channel controller regardless of a high-speed transfer, by performing the control of the data transfer with a microprogram and obtaining the reliability of the transferred data. CONSTITUTION:A microprogram sets the prescribed value to a speed selecting register 5a and a pre-fetch data register respectively before validating a transfer start signal 7 to prepare the transfer of data. When this preparation is over and the signal 7 is validated by the microprogram, the working of a control circuit 5 is started. Then a pre-fetch request permission signal 11 is validated to a transfer request timing generating circuit 5b if no coincidence is obtained from the comparison between the register 5c and a pre-fetch data counter 5d.
申请公布号 JPS58182738(A) 申请公布日期 1983.10.25
申请号 JP19820065331 申请日期 1982.04.21
申请人 HITACHI SEISAKUSHO KK 发明人 SHIBATA YOSHIICHI
分类号 G06F13/38 主分类号 G06F13/38
代理机构 代理人
主权项
地址