发明名称 |
CLOCK SUPPLY SYSTEM OF INTEGRATED CIRCUIT |
摘要 |
<p>PURPOSE:To reduce clock skew, by providing a clock driver in which wirings of clock signals of each phase are wired for each function block and a circuit constant in matching with a load of the clock wirings is set. CONSTITUTION:Functional blocks (FBs) 2 are placed on an LSI chip 1 and clock signals are applied from a clock driver 5 to the FBs 2 via clock wirings 6. Each FB2 is provided with a basic cell 3 and a clock cell 4 for wave shape. The circuit constant of the driver 5 is set to correct a delay in response to the number of loads in the FBs 2 and the length of wires to the FBs 2.</p> |
申请公布号 |
JPS58181322(A) |
申请公布日期 |
1983.10.24 |
申请号 |
JP19820063293 |
申请日期 |
1982.04.16 |
申请人 |
HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK |
发明人 |
KUROSU YASUO;KITATSUME YOSHIAKI;OOHIRA EIJI;FURUKI HITOSHI;FUKAO YOSHIHIRO |
分类号 |
G06F1/10;H03K5/15;(IPC1-7):03K5/15 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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