| 摘要 |
A power output circuit is provided that is protected against latching, due to voltage pulses developed by an indu-ctive load. The circuit comprises a transistor constructed on a monolithic integrated circuit chip, including a grounded semiconductor substrate of one-type conductivity, and collector and emitter regions of opposite-type conductivity located on the substrate and containing opposite-type conductivity modifiers. The collector and emitter regions are separated by a base region of one-type conductivity, and the collector region is coupled to the inductive load.
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