| 摘要 |
PURPOSE:To reduce a cell by employing a pattern forming step for deciding a code and a pattern locus on a wafer obtained by the step for masking to form a gate electrode pattern when forming an ROM of vertical ratioless configuration with IGFET connected in series, thereby reducing the number of mask matching times. CONSTITUTION:When IGFETs are connected in series to form an ROM of vertical ratioless configuration, the pattern is formed as follows. After programming ions are implanted, an oxidized film is etched, a photoresistor is exfoliated, an oxidized film is again covered on the exposed silicon surface, and the oxidized film of the pattern 1 to become a diffused layer and a gate is removed. Then, a gate oxidized film is newly formed. Thus, the pattern 2 of the programming step which does not normally remain stays on the wafer, and the mask of the step for forming a polysilicon pattern 3 is matched to the locus. In this manner, the steps of matching between the steps can be reduced from twice to once. |
