发明名称 STACK MEMORY ADDRESS CONTROLLER
摘要 PURPOSE:To facilitate the resetting of a reread address at the time of retry processing due to the occurrence of a transfer error by resetting automatically the reread address of a stack memory when the retry processing due to the occurrence of the transfer error is performed at the time of back reading operation. CONSTITUTION:When a read signal 12 is inputted in an initial state I wherein a transfer quantity counter 2b and a block quantity counter 2a are both reset, the transfer quantity counter 2b is made to count up and enters a state II. If a transfer error occurs during the read of a block 1 and retry processing is required, a state III is entered, and a retry signal 17 becomes significant and then a next readout request signal 11 becomes significant. At this time, the output of an AND gate 26 is still insignificant, so the block quantity counter 2a does not count up and the transfer quantity counter 2b is reset to enter the state I, so that the data in the block 1 are read out from its head.
申请公布号 JPS62219393(A) 申请公布日期 1987.09.26
申请号 JP19860062708 申请日期 1986.03.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUGITA MASANORI
分类号 G11C7/00;G06F13/00 主分类号 G11C7/00
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