| 摘要 |
In a data receiver (100), sampling circuitry (120, 125) forms samples of a received data signal representing a succession of data symbols. The samples, which are formed at twice the symbol rate, are multiplied by respective ones of a queue of coefficients in a fractionally spaced equalizer (150). Further circuitry (155, 160, 165, 170) forms decisions in response to the resulting products as to the values of the tansmitted symbols and generates error signals. The values of the coefficients are updated in the equalizer in response to the error signals. Timing recovery circuitry (230) within the equalizer periodically identifies the largest of the coefficients and either advances or retards the phase of the sampling circuitry depending on whether that coefficient is or is not within a predetermined portion of the queue. The magnitude of the amount by which the phase is advanced or retarded is determined by the position of the largest coefficient relative to the center of the coefficient queue.
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