| 摘要 |
PURPOSE:To contrive not to cause side etching without reducing the sectional area of a pattern layer by a method wherein the second insulation layer is adhered on the first insulation layer whereon slopes are added at the position of stepwise differences of the pattern layer. CONSTITUTION:The pattern layer 13 is formed on a semiconductor substrate 12, and the insulation layer 14 is adhered. The insulation layer 15 is adhered on the insulation layer 14 whereto slant ion etching has been performed, and a contact hole 16 is kept formed appropriately. Next, a pattern formation is performed by depositing a metallic layer, then a pattern layer 17 above is formed on the insulation layer 15, and accordingly a multi-layer wiring substrate 11 is formed. In the multi-layer wiring substrate 11 obtained in this manner, since the insulation layer 14 of the lower layer is slantly ion-etched, the stewise differences due to the pattern layer 12 becomes gentle, then step cuts do not generate on the pattern layer 17 ?ocated above, and therefore disconnections can be prevented. Even when the insulation layer 14 of the lower layer turns inferior in corrosion resistance at the edge of the pattern layer 13, it can be off-set by the insulation layer 15 located thereabove. |
