| 摘要 |
<p>The design of a system is simplified by making control lines from a microprocessor as small as possible when the frequency-dividing ratio of a programmable divider of a phase-locked loop is controlled by an up/down counter. This circuit has timing control means supplied with a latch signal, data, and a clock signal; data storage means; and an up/down counter. In an up/down counter control circuit, a first level (0 or 1) of the latch signal is detected in a data loading mode based on the control of the timing control means, the data is loaded into the data storage means in synchronism with the clock signal, a second level (1 or 0) of the latch signal is detected in the up/down mode, and the content of the counter is altered in response to the level of the data synchronized with the clock signal.</p> |
