| 摘要 |
PURPOSE:To improve the reliability of data transmission, by using a dead space of a counter pulse transmitted on a clock pulse transmission line for the formation of a reset pulse of a counter at the trasnmission and reception side and making quickly the count values coincident with each other even if they are dissident with each counter. CONSTITUTION:A counter pulse forming one period T1 comprising eight clock pulses and the dead space having the same period T2 is outputted from a circuit 8. Although a terminal voltage of a capacitor of rest circuits 9, 10 repeats increase/decrease during the clock pulse, when the dead space is inputted to mispulse detection circuits 9, 10, the terminal voltage of the capacitor is increased continuously and exceeds a reference voltage of the comparator of ICs 9a, 10a, then a ''0'' signal is outputted from the ICs 9a, 10a, inverted and inputted to counters 6, 7 and the count value is restored to 000=0. In this case, when the dead space is inputted to the counters 6, 7, the counter value is restored to 000=0 and the count is executed again when the next clock pulse is inputted. The operations are repeated, and the count value is corrected after the period T1 at maximum, even if mixcount exists. |
