PIPELINED DIGITAL SIGNAL PROCESSOR USING A COMMON DATA AND CONTROL BUS

摘要

PIPELINED DIGITAL SIGNAL PROCESSOR USING A COMMON DATA AND CONTROL BUS : A digital signal processor arranged for pipelined operation includes a common data and control bus and a source of instructions and data words. An arithmetic section processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination receives the resultant data word from the arithmetic section. Control circuits receive a single normal instruction during each processor cycle for controlling all processing subsections operations. During each processor cycle, each processing subsection performs an operation relating to a different expression than the other processing subsections are performing during that processor cycle. All of the operations controlled by the single normal instruction are executed during a single processor cycle. The common bus is time-shared during every processor cycle for transferring the single normal instruction from the source to the control circuits, for transferring data words from the source to the arithmetic section and for transferring the resultant data word from the arithmetic section to the destination.