发明名称 |
ARITHMETIC PROCESSING METHOD |
摘要 |
PURPOSE:To eliminate the need for a storage circuit for saving storing a remainder and an operation instruction and to shorten a processing time, by using a carry FF which sets by a carry generated by 4-bit addition. CONSTITUTION:Data to be processed which is represented in BCD is stored in a storage circuit 5 and a digit of this data is specified by a data pointer 6. This circuit 5 and pointer 6 are connected to an arithmetic device ALU7 through a bus line 10 and this ALU7 connects with an accumulator 8 and the carry FF9 which sets by a carry generated by 4-bit addition. By a control signal from a control circuit 3, the data to be processed is shifted by the accumulator 8 and FF9. The result of the shifting is stored in the original part of the circuit 5 and if there is the remainder, a correcting value generated by a remainder detecting means is added to the low-order digit data, and the sum is stored in the circuit 5 including the carry; and said processing is carried out from the high-order digit to the low-order digit of the data to find the quotient and remainder. |
申请公布号 |
JPS58172750(A) |
申请公布日期 |
1983.10.11 |
申请号 |
JP19820054818 |
申请日期 |
1982.04.01 |
申请人 |
SANYO DENKI KK;TOKYO SANYO DENKI KK |
发明人 |
YAMASHITA NORIO;MATSUZAWA KENJI |
分类号 |
G06F7/496;G06F7/38;G06F7/491;G06F7/493;G06F7/508;G06F7/52 |
主分类号 |
G06F7/496 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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