发明名称 NOISE LIMITING AND ERASING CIRCUIT
摘要 PURPOSE:To limit the noise of a video input, and to improve the S.N ratio of a trailing synchronous separating circuit, etc., by applying a voltage generated by dividing a power supply voltage through resistances to the emitter of an output amplifying transistor (TR), and connecting its base to the cathode of a diode. CONSTITUTION:The diode 9 performs peak rectification and the TR11 operates as a discharging current source. For example, the diode 9 turns on only during a synchronizing signal period and the TR11 allows discharging all the time. In this case, a discharging current flowing through the diode 9 is denoted as IC, and the resistance connected in series to the diode 9 is R10. Then, the diodes 9 and TR13 have voltage drops canceling each other and a TR13 outputs only a noise component greater than the synchronizing signal to send the noise output to an output terminal. When the emitter current IE3 of the TR3 is greater than the IC, a noise current is limited by a current IE3 and the emitter noise level of a TR2 is limited to (IE3-IC)XR10 for a synchronizing peak.
申请公布号 JPS58172073(A) 申请公布日期 1983.10.08
申请号 JP19820053811 申请日期 1982.04.02
申请人 HITACHI SEISAKUSHO KK 发明人 NOMOTO YOSHIHISA;OOKUBO SHIGEYOSHI
分类号 H04N5/213 主分类号 H04N5/213
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