| 摘要 |
PURPOSE:To reduce an error at the extraction of character broadcasting signal to less than a specific value without using a high clock frequency, by using a polyphase clock generation part, automatic data extraction phase discriminating part, and clock phase selection part. CONSTITUTION:A polyphase clock generation part uses buffers 17 and 18 as delay elements and when a reference signal of 5.73MHz is inputted from an input terminal 16 to buffers 17 and 18, a clock of 5.73MHz shifting in phase by the delay time of one buffer is obtained. While polyphase clocks are supplied from the buffers 17 and 18 to a latch 19, a signal STX synchronizing with a bit synchronizing signal is supplied from an input terminal 31. When the signal STY is inputted at some timing, polyphase clocks 23-30 are latched by the output of the latch 19 and inputted as an 8-bit parallel signal to the ROM20. At this time, the clock phase selection part consisting of a multiplexer 21 and an NAND circuit 22 determines 4-bit of the data terminal output of an ROM20 so that the clock 28 is selected among the polyphase clocks. |
