发明名称 PROCESSING CIRCUIT OF DIGITAL SIGNAL
摘要 PURPOSE:To control contrast without changing luminance by setting the center value of amplitude control to an offset value, subtracting the offset value before multiplication, weighting the subtracted value by a 2'S complement multiplier around ''0'', and adding an offset value to the weighted signal by an adder. CONSTITUTION:An input signal 1 consisting of a binary signal having n bits is inputted to a subtracting circuit 2 to subtract an offset value 3 from the input signal. The subtracted result is inputted to the 2'S complement multiplier 4 to set an optional offset value to ''0''. On the other hand, a binary signal indicating the capacity of control is inputted from a factor setting circuit 6 to the 2'S complement multiplier 4 on the basis of a control signal 5. The signal weighted by the multiplier 4 is applied to an adder 7 to add an offset value 8 to the input signal.
申请公布号 JPS58171183(A) 申请公布日期 1983.10.07
申请号 JP19820054273 申请日期 1982.03.31
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SAKASHITA HIROHIKO;YASUMOTO YOSHIO
分类号 H04N5/57;H04N7/24;H04N19/00 主分类号 H04N5/57
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