| 摘要 |
The buffer memory used for providing the operands in the processor consists of two sets of registers (RSA, RSB) which are each followed by an alternately loadable instruction buffer (BF1, BF2) in which the operands or parameters of at least the last machine instruction can be temporarily stored. Furthermore, a first counter (Z1) for marking the instruction buffer in each case loaded last and a second counter (Z2) are provided, the count of which indicates that no, one or both instruction buffers are valid. When a machine error occurs, the contents of the two instruction buffers are written back into the buffer memory register set, beginning with the instruction buffer in each case loaded last, in accordance with the counts of the two counters (Z1, Z2) stopped in the error state. <IMAGE>
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