| 摘要 |
PURPOSE:To contrive the improvement of switching speed and the reduction of occupation area by forming a word line or a bit line of a buried layer by a method wherein a P-N-P load transistor is formed to a vertical type, and the cell is formed into a three-layer structure in a P-N-P-N-type memory cell. CONSTITUTION:A P-layer 3 is superposed by burying an N<+> layer for the word line W- on a P-substrate, then the array direction is isolated by a layer 9 and isolated from peripheral circuits by a layer 8, next a layer 3 is isolated by a layer 6, accordingly transistors Q10-Q'30 are arranged symmetrically. The electrode Es of the N-emitter 4 of the select element Q30 is connected to the bit line BL, then the electrode C of the N-emitter 5 in operation of Q30 and a hold transistor Q20 is connected to the electrode B' of the common P-base to Q'20 and Q'30, and the P-emitter 7 of the load Q10 is connected to the word line W+. Since the loads Q10 and Q'10 are vertical type, hFE is large, and there is less dispersion in manufacture, further the amounts of unnecessary charges accumulated in each node are small. Therefore, the switching speed of the cell is improved. Since the word line W is buried, the occupation area is decreased. |
