| 摘要 |
PURPOSE:To perform the frequency multiplication with good accuracy, by factorizing the value of N into the product of common multiples and obtaining the frequency multiplied by the common multiples, in obtaining the frequency N times the reference frequncy with a phase locked loop. CONSTITUTION:A multiplication circuit 5 consists of a phase difference detector 7, an LPF8, a voltage controlled oscillator 9, and a 1/N1 counter 10, and a multiplication circuit 6 consists of a phase difference detector 11, an LPF12, a voltage controlled oscillator 13, and a 1/N2 counter 14. The circuits 5 and 6 are connected in cascade. The circuits are factorized into plural phase locked loops PLLs as N=N1, N2-Nn, allowing to decrease the rate of multiplication of each PLL and to widen the permissible fluctuation width. The PLLs having wider permissible band are used and connected in cascade to obtain N times multiplication frequency and to widen the permissible band of the reference frequency. |
