发明名称 MIS STATIC RANDOM ACCESS MEMORY
摘要 PURPOSE:To prevent the breakdown of memory due to external noises by a method wherein the voltage of a word line is raised up momentarily over a power source voltage, and thus the voltage level of writing information is enlarged, in a MIS static RAM immediately after writing. CONSTITUTION:A high voltage supplying circuit HVS is formed of transistors (TR) Q25-Q31, a capacitor C1, and a delay circuit DL, and connected to a line driver RB joined to a line decoder RD. A transfer gate for array selection wherein P and N type TR Q15, Q16, Q17 and Q18 are in parallel is provided between the pair of bit lines BL and the pair of data buses DB, and a writing circuit WTC' is formed of an inverter by using P type TR Q23 and Q24 for the load of the BL pair. By this contitution, the voltage of the word line WL is raised up momentarily to a potential over Vcc after finish or wristing. Thereat, since the voltage of the bit line-BL is raised up to approx. Vcc, the voltage of the node B in a memory cell MC is raised up rapidly to approx. Vcc after finish of writing, and accordingly the breakdown of memory due to external noises is difficult to occur.
申请公布号 JPS58169958(A) 申请公布日期 1983.10.06
申请号 JP19820051152 申请日期 1982.03.31
申请人 FUJITSU KK 发明人 AOYAMA KEIZOU;YAMAUCHI TAKAHIKO;SEKI TERUO
分类号 G11C11/412;G11C11/41;G11C11/413;G11C11/418;G11C11/419;H01L21/8244;H01L27/11 主分类号 G11C11/412
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