发明名称 |
MULTIPLE ACCESS MEMORY CELL AND ITS USE IN A MEMORY ARRAY |
摘要 |
A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array. |
申请公布号 |
DE3064712(D1) |
申请公布日期 |
1983.10.06 |
申请号 |
DE19803064712 |
申请日期 |
1980.10.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
SCHLIG, EUGENE STEWART |
分类号 |
G11C8/16;G11C11/411;(IPC1-7):G11C8/00;G11C11/40 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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