| 摘要 |
PURPOSE:To reduce hardware and a load on a program, by providing a first-in first-out register group between processors. CONSTITUTION:When a request for processing is generated, the program of a CPU-A11 writes the factor of the request for processing, a header byte for indicating the number of transfer bytes, and accompanying data successively in the same address. A first-in first-out (FIFO) memory A41 consists of the register group and shifts written contents from the CPU-A11 immediately to the side of an internal bus B22. If significant data is present in the written data, the FIFO register group sends an interruption OR-B to a CPU-B21. Once detecting the interruption OR-B, the CPU-B21 reads the header firstly and confirms the number of necessary bytes to read the header byte and data. Consequently, program control registers and addresses of the memory are decreased in number greatly. |
