| 摘要 |
A successive-approximation type of analog-to-digital converter which, to increase the effective conversion rate, comprises a series of comparison stages C1 -C8 operable, on a pipeline basis, to form respective bits of a digital signal corresponding to a received analog signal. The first stage C1 compares the received analog signal A with a fixed reference VF and, depending on the result of the comparison, generates an appropriate bit value (to register DR1) and passes on to the next stage by means of analog register AR1 either the same value of analog signal or the difference between that value and the reference. Each subsequent stage, apart from the last, carries out the same operation vis- à-vis the analog signal passed to it by the next preceding stage. The last stage C8 carries out a comparison operation and generates a bit value (to register DRS) but of course does not need to pass on any analog signal. The comparison signals fed to the respective stages may be in binary sequence (as shown) or may be all the same in which case an analog signal doubling element is provided between each two adjacent stages (Fig. 2). <IMAGE> |
