| 摘要 |
PURPOSE:To detect easily a faulty module, by connecting in parallel plural memory modules having reading lines common to each other and providing a gate of the reading line of each memory module to apply a disenable signal. CONSTITUTION:Gates 111 and 112 are provided at the output sides of reading line (e)-(h) and (i)-(l) of IC memories 11' and 12' respectively. These gates are controlled by disenable signals. For instance, if the module 11, a chip 21 and a block B have a fault respectively, the reading line of memory data of either one of modules 11' and 12' is disenabled by applying a disenable signal A or B. Then an access is given through the selection line of the other module to detect the faulty area in a state of package. Thus a faulty module can be easily detected. |
