发明名称
摘要 PURPOSE:To restore the synchronism without giving affection to the operation of exsting system, by inhibiting the input of basic clock to the spare system control circuit when the synchronism monitor unit detects out of period of control signal and releasing the inhibit when the restoration of the signal synchronism is detected. CONSTITUTION:The control signal of the unit is produced from the common basic clock CKL to the duplicated control circuits CTLo and CTL1 of the normal and spare systems, and the synchronism of the control signal is monitored with the signal synchronism monitor unit EOR 1. Further, when the unit EOR 1 detects the out of signal synchronism for the control signal, the input of the spare system CTL1 and the clock CLK is inhibited, and the inhibit is released when the restoration of signal synchronism is detected. Thus, the synchronism can be restored without giving effect on the operation of the existing system.
申请公布号 JPS5844259(B2) 申请公布日期 1983.10.01
申请号 JP19770147964 申请日期 1977.12.09
申请人 FUJITSU LTD 发明人 TSUFUKU SEIJI;TAKAHASHI ATSUHISA;TOKUNAGA JUJI
分类号 H04M3/22;G06F1/04;G06F11/00;G06F11/18;H04Q3/54;H04Q3/545 主分类号 H04M3/22
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