发明名称 HIGH-SPEED DATA TRANSFER BUFFER CIRCUIT
摘要 PURPOSE:To facilitate designing, by providing two random access memories and a switching circuit for switching their input and output data. CONSTITUTION:When transmitter and receivers 40 and 4 are enabled by a signal S1, read data from a magnetic disk is written in an RAM32 throgh a controller 56 and the transmitter and receiver 40, and an RAM34 is read to transfer its read data to a main storage through the transmitter and receiver 44, an interface 30, and a common bus 10. For a next sector, a flip-flop 46 is changed over to enable transmitter and receivers 42 and 38. Therefore, the read data from the disk is written in the RAM34 through a controller 56 and the transmitter and receiver 42 and at the same time, the RAM32 is placed in read mode to transfer its read data to the common bus 10 through the transmitter and receiver 38 and interface 30.
申请公布号 JPS58166469(A) 申请公布日期 1983.10.01
申请号 JP19820048637 申请日期 1982.03.26
申请人 FUJITSU KK 发明人 KOBAYASHI MASAAKI
分类号 G06F12/08;G06F3/06 主分类号 G06F12/08
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