| 摘要 |
PURPOSE:To monitor the execution state of a program, by receiving the instruction control signal of an operating processor and address information by a standby processor, and serving them in a main storage device, and outputting them to an output device or the like. CONSTITUTION:In case of the operation monitor mode, when a decoder output line 2000e of a data fetching instruction is set to ''1'', a gate 800g stores contents of a start address setting circuit 700 into a main storage device address register 300b through the timing line of an instruction fetch controlling circuit. Thereafter, a gate 800c is operated at a write data transmission timing, and contents of a buffer register 600 which are fetched beforehand are set to a data register 900 through a gate 800d, and data is transmitted to a main storage device through a data line 4000, and address data is transmitted through an address line 3000b, and address information of the operating processor is saved. A gate 800e is operated when the normal memory access of its own system is executed. |
