发明名称 FAILURE PROCESSING SYSTEM
摘要 PURPOSE:To improve the stability of a system, by relieving devices against failures individually, and suppressing the effect of the failures, when the failures take place to devices connected to a central processing device via a common bus. CONSTITUTION:When a failed device is an important device in the operation of on-line system such as a main storage device 5, failure information is stored and the system is restarted from a fixed address. When the failed device is not the important part of the operation of the on-line system such as a channel controller 7, an instruction inhibiting the interruption of the device 7 to the failure is transmitted to a failure detection circuit 4. In this interruption inhibiting instruction, the address of a device being a failure is written in an interruption inhibition address storage circuit 13 of the circuit 4. Thus, even if no response due to the failure of the device 7 takes place for many times, since no interruption is given to the central processing device 3, no effect is imposed on the on-line processing program.
申请公布号 JPS58165460(A) 申请公布日期 1983.09.30
申请号 JP19820047144 申请日期 1982.03.26
申请人 HITACHI SEISAKUSHO KK 发明人 ASHIHARA KENJI
分类号 H04M3/22;G06F11/00;G06F11/20 主分类号 H04M3/22
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