发明名称 DECODING CIRCUIT
摘要 PURPOSE:To improve error correcting ability even when the number of erasers is three, by providing a register for storing the position of the 3rd eraser. CONSTITUTION:When there are three erasers, position information on the 3rd eraser is stored in an alphak register 23. The details of the three erasers are as shown in a table and when the number of empty erasers epsilone is three, syndromes S0 and S1 are 0 and data is outputted as it is. When the number of empty erasures is two, S0=el and S1=elalphal (l: i, j, or k); when the output of a driving circuit 15 is compared by a comparing circuit 25 with the outputs of an alphai register 6, alphaj register 7, and alphak register 23, they are often coincident and a coincidence signal appears at an output terminal 26. In this case, the coincident alpha is a main eraser epsilonT and its error extent is outputted as the syndrome S0 to an output terminal 18, thereby making a correction. When there is one or no empty eraser, deletion processing is carried out.
申请公布号 JPS58164347(A) 申请公布日期 1983.09.29
申请号 JP19820046622 申请日期 1982.03.24
申请人 MITSUBISHI DENKI KK 发明人 OONISHI TAKESHI;ISHIDA SADANOBU;ISHIDA MASAYUKI;SUGANO HIROSHI;KAWARABAYASHI SHIGEYUKI;INOUE TOORU;SUGIYAMA YASUO
分类号 H03M13/00;G11B20/18;H04L1/00 主分类号 H03M13/00
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